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线程束Warp

线程束 (Warp) 是一组被共同调度并并行执行的线程线程。一个线程束中的所有线程都被调度到单个流式多处理器 (SM) 上执行。而单个 SM 通常会执行多个线程束，至少会运行来自同一个协作线程数组（也称为线程块）的所有线程束。

线程束是 GPU 上典型的执行单元。在正常执行过程中，线程束的所有线程会并行执行相同的指令，这就是所谓的 "单指令多线程" 或 SIMT 模型。当线程束中的线程因执行不同指令而产生分支（也称为线程束分歧）时，性能通常会急剧下降。

从技术上讲，线程束大小是一个依赖于硬件的常数，但在实际应用中（以及本术语表的其他部分），其大小为32。

当一个线程束被分配指令后，通常无法在单个时钟周期内获得结果，因此无法立即执行依赖该结果的后续指令。这一点在从全局内存（通常位于芯片之外）读取数据时尤为明显，但某些算术指令也存在类似情况（请参阅 CUDA C++ 最佳实践指南了解具体指令的时钟周期结果表）。

若线程束的下一条指令因操作数未就绪而延迟执行，则称其处于停滞(stalled) 状态。

当多个线程束被调度到同一个 SM 上时，线程束调度器不会等待前一条指令的结果返回，而是选择另一个可执行的线程束执行。这种延迟隐藏机制是 GPU 实现高吞吐量并确保执行期间所有核心始终有任务可处理的方式。因此，最大化调度到每个 SM 上的线程束数量通常是有益的，确保始终有符合条件的线程束供 SM 运行。线程束被分配指令的周期比例称为发射效率。线程束调度中的并发程度称为占用率。

线程束实际上并不是 CUDA 编程模型的线程层次结构中的一部分。相反，它们是在 NVIDIA GPU 上实现该模型的实现细节。从这个意义上说，它们有点类似于 CPU 中的缓存行：一种您不直接控制且不需要考虑程序正确性的硬件特性，但对于实现最佳性能很重要。

“Warp” 一词的命名源自编织工艺，根据 Lindholm 等人，2008 论文所述，编织是 "最早的并行线程技术"。其他 GPU 编程模型中与线程束等效的概念包括 WebGPU 中的subgroups、DirectX 中的waves 以及 Metal 中的simdgroups。

英文原文(Modal GPU Glossary)

A warp is a group of threads that are scheduled together and execute in parallel. All threads in a warp are scheduled onto a single Streaming Multiprocessor (SM). A single SM typically executes multiple warps, at the very least all warps from the same Cooperative Thread Array, aka thread block.

Warps are the typical unit of execution on a GPU. In normal execution, all threads of a warp execute the same instruction in parallel — the so-called "Single-Instruction, Multiple Thread" or SIMT model. When the threads in a warp split from one another to execute different instructions, also known as warp divergence, performance generally drops precipitously.

Warp size is technically a machine-dependent constant, but in practice (and elsewhere in this glossary) it is 32.

When a warp is issued an instruction, the results are generally not available within a single clock cycle, and so dependent instructions cannot be issued. While this is most obviously true for fetches from global memory, which generally go off-chip, it is also true for some arithmetic instructions (see the CUDA C++ Best Practices Guide for a table of results per clock cycle for specific instructions).

A warp whose next instruction is delayed by missing operands is said to be stalled.

Instead of waiting for an instruction's results to return, when multiple warps are scheduled onto a single SM, the Warp Scheduler will select another warp to execute. This latency-hiding is how GPUs achieve high throughput and ensure work is always available for all of their cores during execution. For this reason, it is often beneficial to maximize the number of warps scheduled onto each SM, ensuring there is always an eligible warp for the SM to run. The fraction of cycles on which a warp was issued an instruction is known as the issue efficiency. The degree of concurrency in warp scheduling is known as occupancy.

Warps are not actually part of the CUDA programming model's thread hierarchy. Instead, they are an implementation detail of the implementation of that model on NVIDIA GPUs. In that way, they are somewhat akin to cache lines in CPUs: a feature of the hardware that you don't directly control and don't need to consider for program correctness, but which is important for achieving maximum performance.

Warps are named in reference to weaving, "the first parallel thread technology", according to Lindholm et al., 2008. The equivalent of warps in other GPU programming models include subgroups in WebGPU, waves in DirectX, and simdgroups in Metal.

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