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寄存器Registers

寄存器是内存层次结构中与单个线程相关联的内存（左图）。改编自 NVIDIA 的 CUDA Refresher: The CUDA Programming Model 和 NVIDIA CUDA C++ Programming Guide 中的图表。

内存层次结构的最底层是寄存器，用于存储由单个线程操作的信息。

寄存器中的值通常存储在流式多处理器 (SM) 的寄存器文件中，但也可能溢出到 GPU RAM 中的全局内存，这会带来显著的性能损失。

与 CPU 编程类似，这些寄存器不能通过高级语言（如 CUDA C）直接操作。它们仅对底层语言可见，如并行线程执行 (PTX)。它们通常由 ptxas 等编译器管理。编译器的目标之一是限制每个线程使用的寄存器空间，以便可以将更多线程块同时调度到单个 SM 中，从而提高占用率。

PTX 指令集架构中使用的寄存器记录在此处。据我们所知，SASS 中使用的寄存器则没有公开文档。

英文原文(Modal GPU Glossary)

associated with individual threads (left). Modified from diagrams in NVIDIA's CUDA Refresher: The CUDA Programming Model and the NVIDIA CUDA C++ Programming Guide.](themed-image://cuda-programming-model.svg)

At the lowest level of the memory hierarchy are the registers, which store information manipulated by a single thread.

The values in registers are generally stored in the register file of the Streaming Multiprocessor (SM), but they can also spill to the global memory in the GPU RAM at a substantial performance penalty.

As when programming CPUs, these registers are not directly manipulated by high-level languages like CUDA C. They are only visible to a lower-level language, here Parallel Thread Execution (PTX). They are typically managed by a compiler like ptxas. Among the compiler's goals is to limit the register space used by each thread so that more thread blocks can be simultaneously scheduled into a single SM, increasing occupancy.

The registers used in the PTX instruction set architecture are documented here. The registers used in SASS are not, to our knowledge, documented.

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